Double-frequency jitter provoked by nonlinear phase detection in master-slave networks

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dc.contributor.authorPiqueira J.R.C.
dc.contributor.authorCaligares A.Z.
dc.contributor.authorMonteiro L.H.A.
dc.date.accessioned2024-03-13T01:41:33Z
dc.date.available2024-03-13T01:41:33Z
dc.date.issued2006
dc.description.abstractNonlinear phase-detectors produce double-frequency jitter in OWMS (One-Way Master-Slave) chain network for clock distribution systems. This work studies the case of a master-slave architecture with the slave nodes composed of phase-locked loops (PLL) with nonlinear phase detectors. This network is modeled and simulated in order to compare the results with ITU-T standards.
dc.description.firstpage52
dc.description.lastpage54
dc.identifier.urihttps://dspace.mackenzie.br/handle/10899/37739
dc.relation.ispartofProceedings of the Fourth IASTED International Conference on Circuits, Signals, and Systems, CSS 2006
dc.rightsAcesso Restrito
dc.subject.otherlanguageClock signal
dc.subject.otherlanguageDouble-frequency jitter
dc.subject.otherlanguageMaster-slave
dc.subject.otherlanguageNetwork
dc.subject.otherlanguagePhase-locked loop
dc.subject.otherlanguageSynchronization
dc.titleDouble-frequency jitter provoked by nonlinear phase detection in master-slave networks
dc.typeArtigo de evento
local.scopus.citations0
local.scopus.eid2-s2.0-38349183014
local.scopus.subjectClock distribution systems
local.scopus.subjectDouble-frequency jitter
local.scopus.subjectMaster-slave networks
local.scopus.subjectNonlinear phase-detectors
local.scopus.subjectPhase-locked loops (PLL)
local.scopus.updated2024-05-01
local.scopus.urlhttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=38349183014&origin=inward
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